Modern semiconductor packages are formed from multiple stacked material layers that may include numerous active devices electrically coupled together by conductive metal interconnects and lines. Interconnect structures comprising metallization lines such as copper connect various components of semiconductor integrated circuits (ICs). The metallization lines within each interconnect layer are formed in an interlayer dielectric (ILD) material such as a low-k dielectric. The ILD material electrically isolates metallization lines from one another within each level and in adjacent levels of interconnect structures.
Back end-of-line (“BEOL”) fabrication processes are used to create an intricate network of conductive interconnects in each layer and between the multiple layers. Damascene processes including single damascene process and dual-damascene process are routinely used for fabricating multi-level interconnect structures. In a damascene process, trenches and via holes are made inside and through an ILD layer, and filled with a conductive material, such as copper (Cu) or a Cu-based alloy, to create metallization lines and vertical conductive paths (vias) between adjacent layers.